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厂商: Xlinx
内核: Dual-core ARM Cortex-A9 MPCore
运输时间: 3-15天
重量: 0.1 kg

数量: - + 个(库存个)
批量购买请联系: chinasales@embest-tech.com
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PicoZed is a highly flexible, rugged, System-On-Module (SOM), that is based on the Xilinx Zynq®-7000 All Programmable (AP) SoC. It offers designers the flexibility to migrate between the 7010, 7015, 7020, and 7030 Zynq-7000 AP SoC devices in a pin-compatible footprint.

The PicoZed module contains the common functions required to support the core of most SoC designs, including memory, configuration, Ethernet, USB, and clocks. It provides easy access to over 100 user I/O pins through three I/O connectors on the backside of the module. These connectors also support access to dedicated interfaces for Ethernet, USB, JTAG, power and other control signals, as well as the GTP/GTX transceivers on the 7015/7030 models.

The transceiver based 7015 and 7030 versions of PicoZed are a superset of the 7010/7020 version, adding four high-speed serial transceiver ports to the I/O connectors. Designers can simply design their own carrier card, plug-in PicoZed, and start their application development with a proven Zynq-7000 All Programmable SoC sub-system.

Key Features

  • SoC options

    • XC7Z010-1CLG400

    • XC7Z020-1CLG400

    • XC7Z015-1CLG485

    • XC7Z030-1SBG485

  • Memory

    • 1 GB of DDR3 SDRAM    

    • 128 Mb of QSPI Flash

    • 8 GB eMMC

  • Communications

    • 10/100/1000 Ethernet PHY    

    • USB 2.0 PHY

    • User I/O (via three board-to-board connectors)    

  • 7Z010 Version

    • 113 User I/O (100 PL, 13 PS MIO)

    • PL I/O configurable as up to 48 LVDS pairs or 100 single-ended I/O

  • 7Z015 Version                 

    • 4 GTP Transceivers        

    • PL I/O configurable as up to 65 LVDS pairs or 135 single-ended I/O        

    • 148 User I/O (135 PL, 13 PS MIO)        

  • 7Z020 Version                      

    • 138 User I/O (125 PL, 13 PS MIO)        

    • PL I/O configurable as up to 60 LVDS pairs or 125 single-ended I/O    

  • 7Z030 Version                      

    • 148 User I/O (135 PL, 13 PS MIO)        

    • PL I/O configurable as up to 65 LVDS pairs or 135 single-ended I/O        

    • 4 GTX Transceivers    

  • Other

    • JTAG configuration port accessible via I/O connectors    

    • PS JTAG pins accessible via I/O connectors    

    • 33.33 MHz oscillator

  • Software

    • Linux BSP and reference design


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